Research on Delta-Sigma Modulators for High-Performance Analog-to-Digital Conversion

Abstract

본 논문에서는 고성능의 아날로그-디지털 변환을 위한 고해상도 및 넓은 대역폭을 갖는 델타-시그마 변조기의 설계 기법들에 대해서 연구하였다. 사물인터넷과 차량용 반도체의 폭발적인 수요로 인해 아날로그-디지털 변환기의 역할이 더욱 중요하게 되었다. 사물인터넷 기기와 차량용 반도체에는 고해상도 아날로그-디지털 변환기가 필요하다. 또한 사물인터넷 기기의 통진 시스템에는 넓은 대역폭을 갖는 아날로그-디지털 변환기가 필요하다. 델타-시그마 아날로그-디지털 변환기는 고해상도 및 넓은 대역폭이 필요한 응용분야에 적용될 수 있기 때문에 꾸준히 성장할 것으로 예상된다.

첫 번째 연구에서는 고해상도 응용분야에 적용할 수 있는 피드포워드 구조를 사용한 단일-비트 4차 델타-시그마 변조기를 소개하였다. 제안된 연산 트랜스컨덕턴스 증폭기는 기존 설계 방식들에 비해 높은 전력 효율, 넓은 대역폭 및 높은 DC 이득을 제공하는 피드포워드 증폭기 방식을 적용하였습니다. 초퍼-안정화 설계 기법을 첫 번째 적분기에 적용되어 트랜지스터에서 주파수에 반비례하는 1/f 노이즈를 제거했다. 설계된 델타-시그마 변조기는 0.35 µm 표준 CMOS (complementary metal-oxide-semiconductor) 공정을 이용하였다. 본 델타-시그마 변조기의 오버샘플링 비율은 128, 샘플링 주파수는 128 kHz이다. 500 Hz의 신호 대역폭에 대해 측정된 델타-시그마 변조기의 SNR (signal-to-noise ratio) 은 100.3 dB이고 SNDR (signal-to-noise-plus-distortion ratio) 은 98.5 dB이다. 3.3 V 전원 전압에서 전체 전력 소모는 99 µW이고 전체 칩 면적은 0.27 mm2이다.

두 번째 연구에서는 넓은 해상도 응용분야에 적용할 수 있는 피드포워드 구조를 사용한 4-비트 2-2 MASH (multi-stage noise-shaping) 델타-시그마 변조기를 소개하였다. 첫 번째 적분기는 기존의 switched-capacitor 방식 대신 hybrid switching 적분기를 사용하여 시스템의 front-end 회로의 부하 영향을 줄였다. 피드포워드 구조에는 일반적으로 넓은 대역폭과 넓은 swing 범위를 갖는 증폭기로 구성된 active 가산기가 필요하다. Adder-less 적분기를 델타-시그마 변조기 루프 필터에 구현함으로써 active 가산기를 제거하였다. 본 델타-시그마 변조기의 오버샘플링 비율은 16, 샘플링 주파수는 160 MHz이다. 5 MHz의 신호 대역폭에 대해 측정된 델타-시그마 변조기의 SNR은 82.4 dB이고 SNDR은 78.1 dB이다. 1.8 V 전원 전압에서 전체 전력 소모는 26 mW이고 전체 칩 면적은 0.67 mm2이다.|In this dissertation, the design techniques of high-resolution and wide-bandwidth deltasigma modulator (DSM) for high-performance analog-to-digital conversion are presented. The explosive demand for the Internet of Things (IoT) and automotive semiconductors is making analog-to-digital converters (ADCs) more important. High-resolution ADCs are required for sensors in IoT devices and automotive semiconductors. Also, wide-bandwidth ADCs are required for communication systems between IoT devices. A delta-sigma ADC

is expected to grow steadily because it can meet high-resolution and wide-bandwidth applications. The first research describes a single-bit fourth-order DSM with a feedforward structure for high-resolution applications. The proposed operational transconductance amplifier (OTA) uses a feedforward amplifier scheme that provides high-power efficiency, a wider bandwidth, and a higher DC gain compared to conventional designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor,

which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm standard complementary metal-oxide-semiconductor (CMOS) technology. The prototype DSM has an oversampling ratio (OSR) of 128 and a 128 kHz sampling frequency. The prototype DSM measured signal-to-noise ratio (SNR) is 100.3 dB, and the signal-to-noise-plus-distortion ratio (SNDR) is 98.5 dB for a signal bandwidth of 500 Hz.

The measured total power consumption is 99 µW at a 3.3 V supply voltage, and the chip core size is 0.27 mm

2.The second research describes a 4-bit 2-2 multi-stage noise-shaping (MASH) DSM with a feedforward structure for wide-bandwidth applications. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a hybrid switching integrator instead of the conventional switched-capacitor method. In the multi-bit design, the feedforward structure requires an active adder, which is generally implemented with a

wide-bandwidth and a wide-swing range amplifier. In this DSM, the active adder is eliminated, and an adder-less integrator is implemented in the loop filter. Thus, the modulator power consumption, silicon area, and design complexity are significantly reduced. The designed DSM was implemented using 0.18 µm standard CMOS technology. The DSM has an OSR of 16 and a 160 MHz sampling frequency. The prototype DSM measured SNR is

82.4 dB, and the SNDR is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2; In this dissertation, the design techniques of high-resolution and wide-bandwidth deltasigma modulator (DSM) for high-performance analog-to-digital conversion are presented. The explosive demand for the Internet of Things (IoT) and automotive semiconductors is making analog-to-digital converters (ADCs) more important. High-resolution ADCs are required for sensors in IoT devices and automotive semiconductors. Also, wide-bandwidth ADCs are required for communication systems between IoT devices. A delta-sigma ADC

is expected to grow steadily because it can meet high-resolution and wide-bandwidth applications. The first research describes a single-bit fourth-order DSM with a feedforward structure for high-resolution applications. The proposed operational transconductance amplifier (OTA) uses a feedforward amplifier scheme that provides high-power efficiency, a wider bandwidth, and a higher DC gain compared to conventional designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor,

which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm standard complementary metal-oxide-semiconductor (CMOS) technology. The prototype DSM has an oversampling ratio (OSR) of 128 and a 128 kHz sampling frequency. The prototype DSM measured signal-to-noise ratio (SNR) is 100.3 dB, and the signal-to-noise-plus-distortion ratio (SNDR) is 98.5 dB for a signal bandwidth of 500 Hz.

The measured total power consumption is 99 µW at a 3.3 V supply voltage, and the chip core size is 0.27 mm

2.The second research describes a 4-bit 2-2 multi-stage noise-shaping (MASH) DSM with a feedforward structure for wide-bandwidth applications. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a hybrid switching integrator instead of the conventional switched-capacitor method. In the multi-bit design, the feedforward structure requires an active adder, which is generally implemented with a

wide-bandwidth and a wide-swing range amplifier. In this DSM, the active adder is eliminated, and an adder-less integrator is implemented in the loop filter. Thus, the modulator power consumption, silicon area, and design complexity are significantly reduced. The designed DSM was implemented using 0.18 µm standard CMOS technology. The DSM has an OSR of 16 and a 160 MHz sampling frequency. The prototype DSM measured SNR is

82.4 dB, and the SNDR is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2