4 0

Enhancement of the electrical characteristics for 3D NAND flash memory devices through modified cell structure

Title
Enhancement of the electrical characteristics for 3D NAND flash memory devices through modified cell structure
Other Titles
변형된 셀 구조를 통한 3차원 낸드 플래시 메모리 소자의 전기적 특성 향상
Author
이연규
Alternative Author(s)
이연규
Advisor(s)
김태환
Issue Date
2020-02
Publisher
한양대학교
Degree
Master
Abstract
Entering the 4th Industrial Revolution, the growth of artificial intelligence, the Internet of Things, big data, and mobile has led to an increasing demand for solid state drives, which has led to growing interest in NAND flash memory. As a result, the mobile electronics market demand for NAND flash memory with greater storage capacity and faster performance speeds has increased. However, two- dimensional (2D) NAND flash memory devices have encountered inherent problems due to scaling down behaviors such as cell-to-cell interference, unscalable dielectrics, and leakage current. Three- dimensional (3D) NAND flash memory devices not only have overcome these electrical limitations of 2D NAND flash memory devices, but also have improved device performances including faster program operation speed, erase operation speed, read operation speed, and lower power consumption in comparison with 2D NAND flash memory devices. However, interference problems due to the scaling down of 3D NAND flash memory devices still exists, and the occurrence the interference can be categorized into two main causes. One cause of the interference in 3D NAND flash memory devices is the charge storage interference, which occurs by the charges trapped in the spacer. The other cause is the pass voltage (Vpass) interference, which occurs between adjacent cells within the same word line. Recently, many studies regarding the interference of 3D NAND flash memory devices have been performed to improve device performance focusing on system perspective behaviors. However, very few investigations focusing on reducing Vpass interference in 3D NAND flash memories with a novel gate structure have been conducted. In this paper, the electrical characteristics for 3D NAND flash memory devices with a modified cell structure in the gate region were simulated by using a 3D technology computer-aided design simulation tool to improve their Vpass interference. The electrical characteristics of the current-voltage (I-V) curves and electron densities at program, erase, and read operations of the proposed 3D NAND flash memory devices with gate lengths of 20 and 40 nm, and various Vpass values were investigated.|4차 산업혁명시대에 접어들면서 인공 지능, 사물 인터넷, 빅데이터, 모바일의 성장으로 solid state drive에 대한 수요가 증가하여 NAND 플래시 메모리에 대한 관심이 커지고 있다. 그 결과, 더 큰 저장 용량과 더 빠른 동작 속도를 갖는 NAND 플래시 메모리에 대한 모바일 전자 시장의 수요가 증가하고 있다. 하지만, 2차원(2D) NAND 플래시 메모리는 셀 간 간섭, 유전체의 집적화 한계, 누설 전류와 같은 집적화로 인한 문제가 존재한다. 3차원(3D) NAND 플래시 메모리는 2D NAND 플래시 메모리의 전기적 한계를 극복했을 뿐만 아니라, Program / Erase 동작 속도, Read 동작 속도 향상 및 낮은 소비 전력을 갖는다. 그러나 3D NAND 플래시 메모리의 집적화로 인한 간섭 문제는 여전히 존재하며, 간섭의 원인으로는 크게 두 가지로 분류할 수 있다. 3D NAND 플래시 메모리의 간섭 원인 중 한 가지는 저장된 전하에 의한 간섭으로, 스페이서에 갇힌 전하에 의해 발생한다. 다른 원인은 동일한 워드 라인 내의 인접한 셀 사이에서 발생하는 통과 전압(Vpass) 간섭이다. 최근에 시스템 관점 동작에 초점을 둔 장치 성능을 향상시키기 위해 3D NAND 플래시 메모리의 간섭에 관한 많은 연구가 진행되었다. 그러나 구조적 변화를 통해 3D NAND 플래시 메모리에서 Vpass 간섭을 감소시키는 것에 초점을 둔 연구는 거의 이루어지지 않았다. 본 연구에서는 게이트 영역에서 수정 된 셀 구조를 갖는 3D NAND 플래시 메모리의 전기적 특성을 3D 시뮬레이션 툴을 사용하여 시뮬레이션하여 Vpass 간섭에 대해 기술하였다. 게이트 길이가 20 및 40 nm 인 제안 된 3D NAND 플래시 메모리 장치를 다양한 Vpass 값을 인가하여 Program / Erase 및 Read 작업에서 전류-전압 (I-V) 곡선 및 전자 밀도의 전기적 특성이 변화하는 것을 확인 하였고, 간섭에 의한 효과가 개선됨을 확인하였다.
Entering the 4th Industrial Revolution, the growth of artificial intelligence, the Internet of Things, big data, and mobile has led to an increasing demand for solid state drives, which has led to growing interest in NAND flash memory. As a result, the mobile electronics market demand for NAND flash memory with greater storage capacity and faster performance speeds has increased. However, two- dimensional (2D) NAND flash memory devices have encountered inherent problems due to scaling down behaviors such as cell-to-cell interference, unscalable dielectrics, and leakage current. Three- dimensional (3D) NAND flash memory devices not only have overcome these electrical limitations of 2D NAND flash memory devices, but also have improved device performances including faster program operation speed, erase operation speed, read operation speed, and lower power consumption in comparison with 2D NAND flash memory devices. However, interference problems due to the scaling down of 3D NAND flash memory devices still exists, and the occurrence the interference can be categorized into two main causes. One cause of the interference in 3D NAND flash memory devices is the charge storage interference, which occurs by the charges trapped in the spacer. The other cause is the pass voltage (Vpass) interference, which occurs between adjacent cells within the same word line. Recently, many studies regarding the interference of 3D NAND flash memory devices have been performed to improve device performance focusing on system perspective behaviors. However, very few investigations focusing on reducing Vpass interference in 3D NAND flash memories with a novel gate structure have been conducted. In this paper, the electrical characteristics for 3D NAND flash memory devices with a modified cell structure in the gate region were simulated by using a 3D technology computer-aided design simulation tool to improve their Vpass interference. The electrical characteristics of the current-voltage (I-V) curves and electron densities at program, erase, and read operations of the proposed 3D NAND flash memory devices with gate lengths of 20 and 40 nm, and various Vpass values were investigated.
URI
http://dcollection.hanyang.ac.kr/common/orgView/000000111301http://repository.hanyang.ac.kr/handle/20.500.11754/123297
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > NANOSCALE SEMICONDUCTOR ENGINEERING(나노반도체공학과) > Theses (Master)
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE