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Time Division Multiplexing based Test Access for Stacked ICs

Title
Time Division Multiplexing based Test Access for Stacked ICs
Author
박성주
Keywords
3D test access architecture; design-fortestability; stacked-ICs
Issue Date
2019-02
Publisher
대한전자공학회
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 19, No. 1, Page. 87-96
Abstract
The test cost and complexity of stacked ICs (SICs) are higher than those of 2D-ICs because an SIC is tested at more stages before shipping. The existing test access architectures and their optimization techniques for SICs underutilize the tester-channel frequency because the test data is shifted at low scan-shift frequency due to test power constrain. Moreover, the wafer-level test frequency is constrained by limited probe-pin to pad contact current; however, the package-level test can be performed at a higher frequency yet lower than the tester-channel frequency offered by the testers. Therefore, we present a time-multiplexed test access architecture for SICs that leverages the tester-channel frequency at both the wafer-level and package-level tests. Unlike exiting architectures, the proposed architecture does not require the knowledge of the number of dies to be stacked and the hierarchical tier of each die. The proposed architecture is discussed for SICs based on IEEE standards 1149.1 and 1500. The experimental results with a synthetic SIC, constructed with ITC’02 benchmark SoCs, show significant reduction in the test time. Furthermore, the analyses based on the test frequency limits and the number of stacked dies show that the proposed architecture scales well with increasing frequency limits and the number of stacked dies.
URI
http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07617315http://repository.hanyang.ac.kr/handle/20.500.11754/121725
ISSN
1598-1657; 2233-4866
DOI
10.5573/JSTS.2019.19.1.087
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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