Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 송윤흡 | - |
dc.date.accessioned | 2019-12-10T06:40:48Z | - |
dc.date.available | 2019-12-10T06:40:48Z | - |
dc.date.issued | 2018-12 | - |
dc.identifier.citation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 18, no. 6, page. 714-722, Special no. SI | en_US |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07581070&language=ko_KR | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/120884 | - |
dc.description.abstract | In this study we proposed the 'Double-Side- Control-Gate'(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the reduction of interference effect. To demonstrate the performance improvement of the proposed architecture, we analyzed cell-to-cell interference in 3-bit multi-cells and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared and estimated benefits expected from the application of DSCG by calculating Cell-to-Cell Distance(CTCD), pass voltage, etc. Lastly, we confirmed the above 90% reduction of the Cell-to-Cell interference using the DSCG structure. | en_US |
dc.description.sponsorship | This work was supported by the research fund of Hanyang University(HY-2017) and Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (NRF-2016M3A7B4910398). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEK PUBLICATION CENTER | en_US |
dc.subject | Vertical channel | en_US |
dc.subject | DSCG | en_US |
dc.subject | polysilicon | en_US |
dc.subject | 3-D memory | en_US |
dc.subject | 3-D block | en_US |
dc.subject | 3-D stacked NAND Flash memory | en_US |
dc.subject | thin film | en_US |
dc.title | Vertical Channel NAND Flash Structure using DSCG(Double-Side-Control-Gate) to Reduce Cell to Cell Interference | en_US |
dc.type | Article | en_US |
dc.relation.no | 6 | - |
dc.relation.volume | 18 | - |
dc.identifier.doi | 10.5573/JSTS.2018.18.6.714 | - |
dc.relation.page | 714-722 | - |
dc.relation.journal | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.contributor.googleauthor | Choi, Seonjun | - |
dc.contributor.googleauthor | Song, Yun-heub | - |
dc.relation.code | 2018010757 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | yhsong2008 | - |
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