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dc.contributor.author송윤흡-
dc.date.accessioned2019-12-10T06:40:48Z-
dc.date.available2019-12-10T06:40:48Z-
dc.date.issued2018-12-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 18, no. 6, page. 714-722, Special no. SIen_US
dc.identifier.issn1598-1657-
dc.identifier.issn2233-4866-
dc.identifier.urihttp://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07581070&language=ko_KR-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/120884-
dc.description.abstractIn this study we proposed the 'Double-Side- Control-Gate'(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the reduction of interference effect. To demonstrate the performance improvement of the proposed architecture, we analyzed cell-to-cell interference in 3-bit multi-cells and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared and estimated benefits expected from the application of DSCG by calculating Cell-to-Cell Distance(CTCD), pass voltage, etc. Lastly, we confirmed the above 90% reduction of the Cell-to-Cell interference using the DSCG structure.en_US
dc.description.sponsorshipThis work was supported by the research fund of Hanyang University(HY-2017) and Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (NRF-2016M3A7B4910398).en_US
dc.language.isoen_USen_US
dc.publisherIEEK PUBLICATION CENTERen_US
dc.subjectVertical channelen_US
dc.subjectDSCGen_US
dc.subjectpolysiliconen_US
dc.subject3-D memoryen_US
dc.subject3-D blocken_US
dc.subject3-D stacked NAND Flash memoryen_US
dc.subjectthin filmen_US
dc.titleVertical Channel NAND Flash Structure using DSCG(Double-Side-Control-Gate) to Reduce Cell to Cell Interferenceen_US
dc.typeArticleen_US
dc.relation.no6-
dc.relation.volume18-
dc.identifier.doi10.5573/JSTS.2018.18.6.714-
dc.relation.page714-722-
dc.relation.journalJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.contributor.googleauthorChoi, Seonjun-
dc.contributor.googleauthorSong, Yun-heub-
dc.relation.code2018010757-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidyhsong2008-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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