Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유창식 | - |
dc.date.accessioned | 2019-12-10T04:49:12Z | - |
dc.date.available | 2019-12-10T04:49:12Z | - |
dc.date.issued | 2018-11 | - |
dc.identifier.citation | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, v. 46, no. 11, page. 2151-2159 | en_US |
dc.identifier.issn | 0098-9886 | - |
dc.identifier.issn | 1097-007X | - |
dc.identifier.uri | https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.2522 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/120722 | - |
dc.description.abstract | A continuous-time linear equalizer (CTLE) for high-speed serial link is presented whose adaptive boosting gain is obtained with the data and edge values sampled by clock and data recovery circuit. The input offset of the serial link receiver is estimated by the data and edge values as well and cancelled by the CTLE. The adaptation of the CTLE boosting gain is immune to the phase error of the clock and data recovery sampling clock, and the cancellation of the input offset is independent of the boosting gain adaptation. The performance of the proposed adaptive CTLE has been evaluated by applying it to a 5-Gb/s serial link receiver implemented in a 65-nm CMOS technology. | en_US |
dc.description.sponsorship | This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (NRF-2016R1D1A1 B03930310) and the Ministry of Trade, Industry, and Energy (MOTIE), Korea under the Industrial Technology Innovation Program (10080285, IP development and standard definition for 8 K/4 K display). The CAD tools were provided by IC Design Education Centre (IDEC). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | WILEY | en_US |
dc.subject | clock and data recovery (CDR) | en_US |
dc.subject | CMOS | en_US |
dc.subject | continuous-time linear equalizer (CTLE) | en_US |
dc.subject | offset cancellation | en_US |
dc.subject | phase locked loop (PLL) | en_US |
dc.title | Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation | en_US |
dc.type | Article | en_US |
dc.relation.no | 11 | - |
dc.relation.volume | 46 | - |
dc.identifier.doi | 10.1002/cta.2522 | - |
dc.relation.page | 2151-2159 | - |
dc.relation.journal | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | - |
dc.contributor.googleauthor | Lim, Baek-Jin | - |
dc.contributor.googleauthor | Yoo, Changsik | - |
dc.relation.code | 2018002570 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | csyoo | - |
dc.identifier.orcid | http://orcid.org/0000-0001-7945-5400 | - |
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