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Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation

Title
Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation
Author
유창식
Keywords
clock and data recovery (CDR); CMOS; continuous-time linear equalizer (CTLE); offset cancellation; phase locked loop (PLL)
Issue Date
2018-11
Publisher
WILEY
Citation
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, v. 46, no. 11, page. 2151-2159
Abstract
A continuous-time linear equalizer (CTLE) for high-speed serial link is presented whose adaptive boosting gain is obtained with the data and edge values sampled by clock and data recovery circuit. The input offset of the serial link receiver is estimated by the data and edge values as well and cancelled by the CTLE. The adaptation of the CTLE boosting gain is immune to the phase error of the clock and data recovery sampling clock, and the cancellation of the input offset is independent of the boosting gain adaptation. The performance of the proposed adaptive CTLE has been evaluated by applying it to a 5-Gb/s serial link receiver implemented in a 65-nm CMOS technology.
URI
https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.2522http://repository.hanyang.ac.kr/handle/20.500.11754/120722
ISSN
0098-9886; 1097-007X
DOI
10.1002/cta.2522
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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