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A f(REF)/5 Bandwidth Type-II Charge-Pump Phase-Locked Loop With Dual-Edge Phase Comparison and Sampling Loop Filter

Title
A f(REF)/5 Bandwidth Type-II Charge-Pump Phase-Locked Loop With Dual-Edge Phase Comparison and Sampling Loop Filter
Author
유창식
Keywords
CMOS; dual-edge phase comparison (DEPC); phase-locked loop (PLL); sampling loop filter (SLF); type-II charge-pump (CP) PLL
Issue Date
2018-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v. 28, no. 9, page. 825-827
Abstract
The bandwidth (BW) of type-II charge-pump (CP) phase-locked loop (PLL) is extended to f(REF)/5 by dual-edge phase comparison (DEPC) to achieve better phase noise suppression of voltage-controlled oscillator. The reference spur that may result from the unequal duty cycles of reference clock and feedback clock is prevented by sampling loop filter (SLF). A prototype 1.25-GHz type-II CP-PLL employing the proposed DEPC and SLF has been implemented in a 65-nm CMOS technology and achieves 50-MHz BW with 250-MHz reference clock. The phase noise is smaller than -121 dBc/Hz at 1-MHz offset from the carrier, and the reference spur is smaller than -58.5 dBc. The type-II CP-PLL consumes 14.9 mW from a 1.2-V supply and occupies 0.107-mm(2) silicon area.
URI
https://ieeexplore.ieee.org/document/8430518http://repository.hanyang.ac.kr/handle/20.500.11754/120104
ISSN
1531-1309; 1558-1764
DOI
10.1109/LMWC.2018.2860282
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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