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Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector

Title
Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector
Author
박재근
Issue Date
2018-08
Publisher
AMER INST PHYSICS
Citation
APPLIED PHYSICS LETTERS, v. 113, no. 5, Article no. 052103
Abstract
We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross point memory cell without a selector from the viewpoints of p(+)- and n(+)-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p(++)-emitter/n(+)-base/p(+)-base/n(++)-emitter or n(++)-emitter/p(+)-base/n(+)-base/p(++)-emitter. The proper p(+)- and n(+)-base-region width (i.e., 160 nm) and p(++)emitter/n(+)-base/p(+)-base/n(++)-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n(++)-emitter and p(+)-base or n(+)-base and p(++)-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than similar to 4 x 10(-4). Published by AIP Publishing.
URI
https://aip.scitation.org/doi/10.1063/1.5040426http://repository.hanyang.ac.kr/handle/20.500.11754/119780
ISSN
0003-6951; 1077-3118
DOI
10.1063/1.5040426
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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