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dc.contributor.author권오경-
dc.date.accessioned2019-11-19T06:20:12Z-
dc.date.available2019-11-19T06:20:12Z-
dc.date.issued2017-01-
dc.identifier.citationELECTRONICS LETTERS, v. 53, no. 1, page. 16-17en_US
dc.identifier.issn0013-5194-
dc.identifier.issn1350-911X-
dc.identifier.urihttps://digital-library.theiet.org/content/journals/10.1049/el.2016.3706-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/112355-
dc.description.abstractA dual correlated double sampling (CDS) scheme, which can be embedded into a successive approximation register (SAR) or SAR/single-slope analogue-to-digital converters (ADCs) for low-noise CMOS imagers without the use of a power-consuming programmable gain amplifier (PGA) is proposed. To reduce the noise of the readout channel, the proposed dual CDS scheme removes the sampling error, which occurs in the capacitor digital-to-analogue converter (DAC), by storing only a reset voltage of the pixel into the capacitor DAC. In addition, without using the PGA, it amplifies the output of the readout channel by controlling the reference voltages of the ADC. The readout channel using the proposed CDS scheme was designed using a 90 nm CMOS imager process technology. The simulation results show that the signal-to-noise-distortion ratio of the readout channel using the proposed dual CDS scheme is 81.8 dB, which is an improvement of 10.8 dB over the digital CDS scheme. In addition, the output of the readout channel is amplified without the use of a PGA.en_US
dc.language.isoenen_US
dc.publisherINST ENGINEERING TECHNOLOGY-IETen_US
dc.subjectanalogue-digital conversionen_US
dc.subjectreadout electronicsen_US
dc.subjectCMOS digital integrated circuitsen_US
dc.subjectdual CDS schemeen_US
dc.subjectSAR-based ADCsen_US
dc.subjectlow-noise CMOS imagersen_US
dc.subjectdual correlated double sampling schemeen_US
dc.subjectsuccessive approximation registeren_US
dc.subjectsingle-slope analogue-to-digital convertersen_US
dc.subjectreadout channelen_US
dc.subjectnoise reductionen_US
dc.subjectcapacitor digital-to-analogue converteren_US
dc.subjectDACen_US
dc.subjectCIS process technologyen_US
dc.subjectsignal-to-noise-distortion ratioen_US
dc.subjectsize 90 nmen_US
dc.titleDual CDS scheme embedded in SAR-based ADCs for low-noise CMOS imagers without a PGAen_US
dc.typeArticleen_US
dc.relation.no1-
dc.relation.volume53-
dc.identifier.doi10.1049/el.2016.3706-
dc.relation.page16-17-
dc.relation.journalELECTRONICS LETTERS-
dc.contributor.googleauthorKim, M. -K.-
dc.contributor.googleauthorHong, S. -K.-
dc.contributor.googleauthorGou, J.-
dc.contributor.googleauthorKwon, O. -K.-
dc.relation.code2017001260-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidokwon-
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COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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