Due to reduced device sizes and threshold voltages, leakage current becomes an important issue in CMOS design. In a CMOS combinational logic circuit, the state of the inputs and thus can be minimized by applying an optimal input when the circuit is idling. In this paper, we present a New Input Vector Control algorithm, called Leakage Minimization by Input vector Control(LMIC) for minimal leakage power. This algorithm finds the minimal leakage vector and reduces leakage current up to 22% on the average, for TSMC 0.18um process parameters. Minimal leakage vectors are very useful in reducing leakage currents in standby mode of operation.