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New Model-based IP-Level Power Estimation for Digital Circuits

Title
New Model-based IP-Level Power Estimation for Digital Circuits
Author
신현철
Issue Date
2005-10
Publisher
대한전자공학회
Citation
ISOCC 2005 Conference, Page. 337 - 340
Abstract
New efficient and effective power estimation techniques have been developed for Intellectual Property(IP)-Level digital circuits. Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-a-Chip(SoC) and increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits are levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of benchmark circuits to illustrate their effectiveness. Experimental results show significant improvement in estimation accuracy and slight improvement in efficiency when compared to those of a well-known existing method[1].
URI
https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01789820http://repository.hanyang.ac.kr/handle/20.500.11754/111653
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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