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dc.contributor.author신현철-
dc.date.accessioned2019-10-30T01:42:19Z-
dc.date.available2019-10-30T01:42:19Z-
dc.date.issued2005-10-
dc.identifier.citationISOCC 2005 Conference, Page. 68 - 71en_US
dc.identifier.urihttps://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01789743-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/111652-
dc.description.abstractAs digital mobile communication becomes popular, data processing capability that includes H.264 and 3D graphics will be essential for future mobile terminals. In this paper, reconfigurable architecture is described, which can perform either notion estimation for H.264 or rendering for 3D graphics. In motion estimation for variable block sizes, disable approximate unit has been designed to make early termination of absolute difference computation when the termination does not affect the performance. In 3D rendering, midline traversal algorithm is used for parallel processing. Memories are partitioned for sharing and selective power shutdown. Processing elements are also shared to reduce the chip area by 7%.-
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.titleReconfigurable Architecture Design for H.264 Motion Estimation and 3D Graphics Renderingen_US
dc.typeArticleen_US
dc.contributor.googleauthorPark, Jeongae-
dc.contributor.googleauthorYoon, Misun-
dc.contributor.googleauthorShin, Hyunchul-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidshin-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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