Minimization of Leakage Current by Using the Genetic Algorithm

Abstract

Leakage current reduction becomes extremely important in the design of CMOS logic circuits. In the past, the leakage power was a small fraction of the dynamic power and thus can be ignored. However, technology scaling enables to integrate huge number of transistors on a chip for higher performance. This comes at the price of increase in both static and dynamic power consumption [1]. Furthermore, threshold voltage reduction increases the leakage current. When a circuit block is idling, one can reduce the leakage power by applying the minimum leakage vecotor. For small-sized problems, exhaustive algorithms can be used to find the optimal solution. For large- sized problems, probabilistic algorithms can be used. Genetic algorithm is a part of evolutionary computing. Genetic algorithms have been used as adaptive algorithms to solve NP-complete problems. In this paper, we minimize the leakage current using the Genetic algorithm.

Keywords: Leakage current, Genetic algorithm, Minimum leakage input vector