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Efficient Interconnect Test Patterns for Crosstalk and Static Faults

Title
Efficient Interconnect Test Patterns for Crosstalk and Static Faults
Author
박성주
Keywords
crosstalk faults; interconnect test; static faults; system-on-chip (SoC)
Issue Date
2006-11
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v. 25, No. 11, Page. 2605-2608
Abstract
This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, 6n patterns are introduced to completely detect and diagnose both static and crosstalk faults, where n is the total number of interconnect nets. Then, more economic 4n+1 patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance.
URI
https://ieeexplore.ieee.org/document/1715444http://repository.hanyang.ac.kr/handle/20.500.11754/108861
ISSN
0278-0070
DOI
10.1109/TCAD.2006.873899
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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