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천이 지연 고장 테스트를 위한 IEEE 1500 래퍼 셀 설계

Title
천이 지연 고장 테스트를 위한 IEEE 1500 래퍼 셀 설계
Other Titles
Design of IEEE 1500 Wrapper Cell For Transition Delay Fault Test
Author
박성주
Issue Date
2006-11
Publisher
대한전자공학회
Citation
대한전자공학회 2006년도 추계학술대회 논문집Ⅱ, Page. 391 - 394
Abstract
As the integration density of System on Chips (SoCs) and the operating speed become increasingly fast, it is crucial to test delay. In order to detect transition delay fault, the test responses must be captured in a system clock cycle after applying sequential test pattern. This paper introduces an IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller to wrapper serial port interface logic, and propose a transition delay fault test. Proposed method can simultaneously test of transition delay fault of IEEE 1500 wrapped cores using different core clocks, has low area overhead, and reduces test time.
URI
http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE06324350&language=ko_KRhttp://repository.hanyang.ac.kr/handle/20.500.11754/108778
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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