Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems

Abstract

This paper presents a new optimization algorithm for designing parallel Cyclic Redundancy Check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead.