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dc.contributor.author박성주-
dc.date.accessioned2019-08-13T07:39:49Z-
dc.date.available2019-08-13T07:39:49Z-
dc.date.issued2006-10-
dc.identifier.citation2006 10th IEEE Singapore International Conference on Communication Systems, Article no. 4085745en_US
dc.identifier.isbn978-142440411-7-
dc.identifier.urihttps://ieeexplore.ieee.org/document/4085745-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/108562-
dc.description.abstractThis paper presents a new optimization algorithm for designing parallel Cyclic Redundancy Check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead.en_US
dc.description.sponsorshipThis work was supported by Brain Korea 21 (BK21) project in Korea.en_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.titleParallel CRC Logic Optimization Algorithm for High Speed Communication Systemsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ICCS.2006.301450-
dc.contributor.googleauthorY., Hyunbean-
dc.contributor.googleauthorS., Jaehoon-
dc.contributor.googleauthorP., Sungju-
dc.contributor.googleauthorP., Changwon-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF COMPUTING[E]-
dc.sector.departmentDIVISION OF COMPUTER SCIENCE-
dc.identifier.pidpaksj-
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COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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