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An Efficient Link Controller for Test Access to IP Core-based Embedded System Chips

Title
An Efficient Link Controller for Test Access to IP Core-based Embedded System Chips
Author
박성주
Keywords
Embedded System; Boundary Scan; SoC Testing; Test Access Mechanism; Wrapper
Issue Date
2007-12
Publisher
SPRINGER-VERLAG BERLIN
Citation
Asia-Pacific Conference on Advances in Computer Systems Architecture; ACSAC 2007: Advances in Computer Systems Architecture, Page. 139-150
Abstract
It becomes crucial to test and verify embedded hardware systems precisely and efficiently. For an embedded System-on-a-Chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test access link configurations. In this paper, a Flag-based Wrapped Core Link Controller (FWCLC) is introduced to enable efficient accessibility to embedded cores as well as seamless integration of IEEE 1149.1 TAPd cores and IEEE 1500 wrapped cores. Compared with other state-of-the-art techniques, our technique requires no modification on each core, less area overhead, and provides more diverse link configurations for design-for-debug as well as design-for-test.
URI
https://link.springer.com/chapter/10.1007/978-3-540-74309-5_15http://repository.hanyang.ac.kr/handle/20.500.11754/107474
ISBN
978-3-540-74309-5; 978-3-540-74308-8
DOI
10.1007/978-3-540-74309-5_15
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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