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Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC

Title
Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC
Author
박성주
Issue Date
2007-10
Publisher
IEEE
Citation
16th Asian Test Symposium (ATS 2007), Page. 193-198
Abstract
This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.
URI
https://ieeexplore.ieee.org/document/4388008http://repository.hanyang.ac.kr/handle/20.500.11754/107169
ISBN
978-0-7695-2890-8
ISSN
1081-7735; 2377-5386
DOI
10.1109/ATS.2007.13
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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