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Logical Operation Based Parallel Decoding Scheme for H.264/AVC CAVLC

Title
Logical Operation Based Parallel Decoding Scheme for H.264/AVC CAVLC
Author
신현철
Keywords
H.264; CAVLC; VLD
Issue Date
2007-10
Publisher
대한전자공학회
Citation
ISOCC 2007 Conference, Page. 177 - 180
Abstract
An effective parallel decoding method has been developed for context-based adaptive variable length coding (CAVLC). Several new ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations are used for fast low power operations, while table look-ups are used for many conventional CAVLC algorithms. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input is simultaneously analyzed. When M is large, decoding rate becomes high at a high area cost. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. For similar decoding rates, our new approach uses 44% less area than the typical conventional method.
URI
http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01789575&language=ko_KRhttp://repository.hanyang.ac.kr/handle/20.500.11754/107085
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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