ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications; ITC-CSCC : 2007, Page. 645 - 646
This paper presents details of the design and implementation of a fully synthesized digital decimation filter that provides time-to-market advantage for delta-sigma analog-todigital converters. This decimation filter is fabricated in 0.25-㎛ CMOS technology with 1.36 ㎡ of active area, and shows 4.4 ㎽ power consumption at a clock rate of 2.8224 ㎒. Experimental results show that this digital decimation filter is suitable for oversampled data converters and can be ported to new processes with fast redesign time since it does not have processdependent ROM or RAM circuits.