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Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits

Title
Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits
Author
신현철
Keywords
low-power design; control signal; power estimation; switching activity
Issue Date
2007-07
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE TRANSACTIONS ON COMMUNICATIONS, v. E90B, No. 7, Page. 1826-1834
Abstract
As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.
URI
https://search.ieice.org/bin/summary.php?id=e90-b_7_1826http://repository.hanyang.ac.kr/handle/20.500.11754/106698
ISSN
0916-8516; 1745-1345
DOI
10.1093/ietcom/e90-b.7.1826
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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