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dc.contributor.author박성주-
dc.date.accessioned2019-05-22T02:58:06Z-
dc.date.available2019-05-22T02:58:06Z-
dc.date.issued2018-04-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 18, No. 2, Page. 218-226en_US
dc.identifier.issn1598-1657-
dc.identifier.urihttp://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07420101-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/105478-
dc.description.abstractScan flip-flop based physically unclonable function (SCAN-PUF) has been proposed to protect integrated circuits (ICs) from security threats such as unauthorized access and IC cloning. In this paper, we propose an efficient SCAN-PUF technique that improves the uniqueness of responses with low cost overhead. The proposed SCAN-PUF first determines an optimal number of power-up state observations and then selects scan flip-flops as the PUF elements (P-ELEMENTs) through a given number of observations. A Bayesian model is adopted to evaluate the reliability of the P-ELEMENTs, and a grouped P-ELEMENT selection method is introduced to obtain more P-ELEMENTs than a predetermined threshold. To evaluate the proposed SCAN-PUF, we observed the power-up states of scan flip-flops from 15 chips fabricated using the 65-nm CMOS technology. The optimal number of observations is determined according to the reliability of the P-ELEMENTs, and the reliability, randomness, and uniqueness of the responses are then analyzed.en_US
dc.description.sponsorshipThis research was partly supported by the MOTIE (Ministry of Trade, Industry & Energy (10052875)) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device and the National Research Foundation of Korea Grant funded by the Ministry of Education, Science and Technology under Grant NRF-2017R1D1A1B03030821.en_US
dc.language.isoen_USen_US
dc.publisher대한전자공학회en_US
dc.subjectBayesian theoremen_US
dc.subjectcounterfeit ICsen_US
dc.subjecthardware securityen_US
dc.subjectphysically unclonable functionen_US
dc.subjectscan designen_US
dc.titleCost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Functionen_US
dc.typeArticleen_US
dc.identifier.doi10.5573/JSTS.2018.18.2.218-
dc.relation.page218-226-
dc.relation.journalJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.contributor.googleauthorKim, Dooyoung-
dc.contributor.googleauthorAnsari, M. Adil-
dc.contributor.googleauthorJung, Jihun-
dc.contributor.googleauthorKim, Jinuk-
dc.contributor.googleauthorPark, Sungju-
dc.relation.code2018010757-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF COMPUTING[E]-
dc.sector.departmentDIVISION OF COMPUTER SCIENCE-
dc.identifier.pidpaksj-
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COLLEGE OF COMPUTING[E](소프트웨어융합대학) > COMPUTER SCIENCE(소프트웨어학부) > Articles
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