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dc.contributor.author박성주-
dc.date.accessioned2019-05-20T07:40:29Z-
dc.date.available2019-05-20T07:40:29Z-
dc.date.issued2008-11-
dc.identifier.citation2008 17th Asian Test Symposium, Article no. 4711607, Page. 289-294en_US
dc.identifier.isbn978-0-7695-3396-4-
dc.identifier.issn1081-7735-
dc.identifier.urihttps://ieeexplore.ieee.org/abstract/document/4711607-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/105030-
dc.description.abstractThis paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core debug supporting logics which can support transaction-based debug. A debug interface unit is also presented to enable debug data transfer through an NoC between an external debugger and a coreunder-debug (CUD). The proposed approach supports debug of designs with multiple clock domains. It also supports collection of trace signatures to facilitate debug of long pattern sequences. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead. We also present simulation result to verify proper operation of the debug components.en_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.subjectdesign-for-debug (DfD)en_US
dc.subjectsystem-on-chip (SoC)en_US
dc.subjectnetwork-on-chip (NoC)en_US
dc.subjectPSMIen_US
dc.titleA Design-for-Debug(DfD) for NoC-Based SoC Debugging via NoCen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ATS.2008.15-
dc.contributor.googleauthorYi, Hyunbean-
dc.contributor.googleauthorPark, Sungju-
dc.contributor.googleauthorKundu, S.-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF COMPUTING[E]-
dc.sector.departmentDIVISION OF COMPUTER SCIENCE-
dc.identifier.pidpaksj-
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COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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