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Scheduling Considering Bit Level Delays

Title
Scheduling Considering Bit Level Delays
Author
신현철
Keywords
bit level delay; chaining; high level synthesis; scheduling
Issue Date
2008-11
Publisher
IEEE
Citation
2008 International SoC Design Conference, Page. 330-333
Abstract
A new scheduling method considering bit level delays for high level synthesis is proposed. Conventional bit level delay computation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit level delay computation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit level delays. Furthermore, multicycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.
URI
https://ieeexplore.ieee.org/abstract/document/4815639http://repository.hanyang.ac.kr/handle/20.500.11754/105028
ISBN
978-1-4244-2598-3
DOI
10.1109/SOCDC.2008.4815639
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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