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dc.contributor.author신현철-
dc.date.accessioned2019-05-20T07:35:21Z-
dc.date.available2019-05-20T07:35:21Z-
dc.date.issued2008-11-
dc.identifier.citation대한전자공학회 2008년 정기총회 및 추계종합학술대회, Page. 449-450en_US
dc.identifier.urihttp://www.dbpia.co.kr/Journal/ArticleDetail/NODE01595891-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/105017-
dc.description.abstractIn this paper, we propose complex gate type structures, for design for debug and repair. When an error is found on a semiconductor chip, we want to fix the error by using the spare cells. Our complex gates based spare cells use 55% less NMOSs and PMOSs on the average, when compared to standard cell NAND gate structures, for ISCAS85 benchmark circuits.en_US
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.titleDFD를 위한 효율적인 콤플렉스 셀 설계en_US
dc.title.alternativeEfficient Complex Cell Design for Design for Debugen_US
dc.typeArticleen_US
dc.contributor.googleauthor신주용-
dc.contributor.googleauthor안레센-
dc.contributor.googleauthor신현철-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidshin-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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