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DFD를 위한 효율적인 콤플렉스 셀 설계

Title
DFD를 위한 효율적인 콤플렉스 셀 설계
Other Titles
Efficient Complex Cell Design for Design for Debug
Author
신현철
Issue Date
2008-11
Publisher
대한전자공학회
Citation
대한전자공학회 2008년 정기총회 및 추계종합학술대회, Page. 449-450
Abstract
In this paper, we propose complex gate type structures, for design for debug and repair. When an error is found on a semiconductor chip, we want to fix the error by using the spare cells. Our complex gates based spare cells use 55% less NMOSs and PMOSs on the average, when compared to standard cell NAND gate structures, for ISCAS85 benchmark circuits.
URI
http://www.dbpia.co.kr/Journal/ArticleDetail/NODE01595891http://repository.hanyang.ac.kr/handle/20.500.11754/105017
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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