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Simulated Annealing을 이용한 FPGA 배치에서의 cooling 계획

Title
Simulated Annealing을 이용한 FPGA 배치에서의 cooling 계획
Other Titles
Cooling schedule for FPGA Placement using Simulated Annealing
Author
신현철
Issue Date
2009-11
Publisher
대한전자공학회
Citation
대한전자공학회 2009년 정기총회 및 추계종합학술대회, Page. 87-88
Abstract
In this paper, we propose a new cooling schedule for placement of Field Programmable Gate Array (FPGA) by using Simulated Annealing. By using the proposed cooling schedule, we obtain improved results, when compared to those of Versatile Place and Route (VPR). Experiment results shows that cost and move number were reduced by 0.3%, 22.8% respectively.
URI
http://www.dbpia.co.kr/Journal/ArticleDetail/NODE01593199http://repository.hanyang.ac.kr/handle/20.500.11754/104219
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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