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A scalable micro wireless interconnect structure for CMPs

Title
A scalable micro wireless interconnect structure for CMPs
Author
이석복
Keywords
Chip multiprocessors; On-chip wireless interconnection network
Issue Date
2009-09
Publisher
ACM
Citation
MobiCom '09 Proceedings of the 15th annual international conference on Mobile computing and networking, Pages 217-228
Abstract
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds to thousands of cores in chip multiprocessors (CMPs), where current interconnect technologies face severe scaling limitations in excessive latency, long wiring, and complex layout. We propose a recursive wireless interconnect structure called the WCube that features a single transmit antenna and multiple receive antennas at each micro wireless router and offers scalable performance in terms of latency and connectivity. We show the feasibility to build miniature on-chip antennas, and simple transmitters and receivers that operate at 100-500 GHz sub-terahertz frequency bands. We also devise new two-tier wormhole based routing algorithms that are deadlock free and ensure a minimum-latency route on a 1000-core on-chip interconnect network. Our simulations show that our protocol suite can reduce the observed latency by 20% to 45%, and consumes power that is comparable to or less than current 2-D wired mesh designs. Copyright 2009 ACM.
URI
https://dl.acm.org/citation.cfm?doid=1614320.1614345http://repository.hanyang.ac.kr/handle/20.500.11754/104092
ISBN
978-160558702-8
DOI
10.1145/1614320.1614345
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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