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dc.contributor.author신현철-
dc.date.accessioned2019-05-13T07:42:16Z-
dc.date.available2019-05-13T07:42:16Z-
dc.date.issued2009-07-
dc.identifier.citation2009 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications, Page. 149-152en_US
dc.identifier.urihttp://www.dbpia.co.kr/Article/NODE01590477-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/104063-
dc.description.abstractTo solve computationally expensive problems, multiple processor SoCs (MPSoCs) are frequently used. Mapping of applications to MPSoC architectures and scheduling of tasks are key problems in system level design of embedded systems. In this paper, iterative zone refinement algorithm is described, in which the tasks in the active zone is simultaneously mapped and scheduled for heterogeneous MPSoC architectures. The tradeoff between run-time and quality of solution is possible by adjusting the number of tasks in the zone. Experimental results show that our method is very effective.en_US
dc.language.isoen_USen_US
dc.publisher대한전자공학회en_US
dc.subjectmappingen_US
dc.subjectschedulingen_US
dc.subjectMulti Processor System on Chip(MPSoC)en_US
dc.subjectBranch and Bounden_US
dc.subjectZone Refiningen_US
dc.titleEffective Mapping and Scheduling for Multi-core Systems, by Using Iterative Zone Refinementen_US
dc.typeArticleen_US
dc.relation.page149-152-
dc.contributor.googleauthorKim, Jongdae-
dc.contributor.googleauthorKim, Soohyun-
dc.contributor.googleauthorShin, Hyunchul-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidshin-
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COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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