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Cycle Accurate Memory Delay Modeling for Off-Chip DRAMs

Title
Cycle Accurate Memory Delay Modeling for Off-Chip DRAMs
Author
신현철
Keywords
memory delay modeling; memory optimization
Issue Date
2009-05
Publisher
대한전자공학회
Citation
대한전자공학회 2009년 SoC학술대회, Page. 255-258
Abstract
MPSoCs are gaining popularity because of its potential to solve computationally expensive problems. MPSoCs frequently use two kinds of memories; on-chip SRAMs and off-chip DRAMs. Processors in multicore systems usually take many clock cycles for the transfer of data to/from off-chip memories which affects the overall system performance. While an on-chip memory operation takes one or two clock cycles, an off-chip memory access takes significantly more number of clock cycles. Therefore, delay modeling for off-chip memories is important to optimize the overall system performance. This paper proposes the cycle accurate delay modeling techniques for finding the exact delays for off-chip memories.
URI
http://www.dbpia.co.kr/Journal/ArticleDetail/NODE01229245http://repository.hanyang.ac.kr/handle/20.500.11754/103949
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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