IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE ELECTRONICS EXPRESS, v. 13, No. 24, Article no. 20160665
A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of -67.9 dB at 10 MHz.