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LDO regulator with high power supply rejection at 10MHz

Title
LDO regulator with high power supply rejection at 10MHz
Author
노정진
Keywords
low-dropout regulator; power supply rejection; negative capacitance; DROP-OUT REGULATOR; CMOS; CANCELLATION
Issue Date
2016-12
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 13, No. 24, Article no. 20160665
Abstract
A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of -67.9 dB at 10 MHz.
URI
https://www.jstage.jst.go.jp/article/elex/13/24/13_13.20160665/_article/-char/ja/http://repository.hanyang.ac.kr/handle/20.500.11754/103036
ISSN
1349-2543
DOI
10.1587/elex.13.20160665
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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