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Time-multiplexed test access architecture for stacked integrated circuits

Title
Time-multiplexed test access architecture for stacked integrated circuits
Author
박성주
Keywords
3D test access architecture; design-for-testability; stacked-ICs; OPTIMIZATION; SOCS; ICS
Issue Date
2016-07
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 13, No. 14, Article no. 20160314
Abstract
Due to ever-increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies, the tester-channel frequency is underutilized for stacked-ICs. Thus, we present a novel time-multiplexed test access architecture for SICs that complies with P1838 and it significant reduces test time, which reduction is observed on a synthetic SIC based on ITC'02 benchmark SoCs.
URI
https://www.jstage.jst.go.jp/article/elex/13/14/13_13.20160314/_article/-char/ja/http://repository.hanyang.ac.kr/handle/20.500.11754/102561
ISSN
1349-2543
DOI
10.1587/elex.13.20160314
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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