3D test access architecture; design-for-testability; stacked-ICs; OPTIMIZATION; SOCS; ICS
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE ELECTRONICS EXPRESS, v. 13, No. 14, Article no. 20160314
Due to ever-increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies, the tester-channel frequency is underutilized for stacked-ICs. Thus, we present a novel time-multiplexed test access architecture for SICs that complies with P1838 and it significant reduces test time, which reduction is observed on a synthetic SIC based on ITC'02 benchmark SoCs.