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Charge sharing based 10T SRAM for low-power

Title
Charge sharing based 10T SRAM for low-power
Author
신현철
Keywords
low-power; 10T; charge sharing; SNM free; single ended
Issue Date
2016-03
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 13, No. 5, Article no. 20151033
Abstract
We propose a novel charge sharing bit-line 10T SRAM for differential read and single ended (SE) write. Decoupled read provides high noise margin. Read bit-lines are not charged to full V-DD, and these share charge for read 1 operation. A new write driver is proposed for SE write which charges the write-bit-line conditionally. Virtual power rail is used to suppress bit-line leakages. Compared with 6T SRAM, charge sharing scheme potentially consumes only 25% read and 50% write dynamic power. Thorough comparisons with 6T at 45 nm node show that the proposed 10T design has 2x read static noise margin, 71% reduction in total read and 48% reduction in total write power.
URI
https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_13.20151033/_article/-char/ja/http://repository.hanyang.ac.kr/handle/20.500.11754/102196
ISSN
1349-2543
DOI
10.1587/elex.13.20151033
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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