신현철
2019-05-20T07:39:07Z
2019-05-20T07:39:07Z
2008-11
2008 International SoC Design Conference, Page. 330-333
978-1-4244-2598-3
https://ieeexplore.ieee.org/abstract/document/4815639
https://repository.hanyang.ac.kr/handle/20.500.11754/105028
A new scheduling method considering bit level delays for high level synthesis is proposed. Conventional bit level delay computation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit level delay computation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit level delays. Furthermore, multicycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.
en_US
IEEE
bit level delay
chaining
high level synthesis
scheduling
Scheduling Considering Bit Level Delays
Article
10.1109/SOCDC.2008.4815639
Kim, Jiwoong
Shin, Hyunchul
E
COLLEGE OF ENGINEERING SCIENCES[E]
DIVISION OF ELECTRICAL ENGINEERING
shin