권오경
2017-08-04T06:19:41Z
2017-08-04T06:19:41Z
2015-10
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v. 62, NO 10, Page. 932-936
1549-7747
1558-3791
http://ieeexplore.ieee.org/document/7161297/?arnumber=7161297&tag=1
http://hdl.handle.net/20.500.11754/28308
This brief proposes a small-area and energyefficient 12-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors with a column-parallel readout structure. The proposed SA-ADC, which uses only a 6-bit capacitor digital-to-analog converter (DAC) for residue sampling, reduces the capacitor area to 1/64th of that for the 12-bit capacitor DAC and adopts the scaled reference voltages for 12-bit conversion. It also achieves 88% lower switching energy of the capacitor DAC compared with the 12-bit SA-ADC with split capacitor structure. A foreground digital calibration is employed to compensate for the linearity error caused by the inaccurately scaled reference voltages. A test chip, which has 100 readout channels with the proposed SA-ADC, is fabricated using a 0.18-mu m CMOS process. The measurement results show that the proposed SA-ADC with the proposed digital calibration has differential nonlinearity (DNL) of -0.8/+1.7 LSB and integral nonlinearity (INL) of -2.3/+2.4 LSB, and without the calibration, it has DNL of -1/+14.9 LSB and INL of -15.8/+12.7 LSB. In addition, a digital correlated double sampling method improves the standard deviation of the readout channel outputs from 62.1 to 1.4 LSB.
This work was a result of the Industrial and Educational Cooperative R&D Program between Hanyang University and SK Hynix Semiconductor Inc., and the chip fabrication was supported by IC Design Education Center (IDEC). The authors would like to thank J. Gou and S.-D. Yoo of SK Hynix Semiconductor Inc. for their useful discussion.
en
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
CMOS image sensor (CIS)
column-parallel readout
foreground digital calibration
successive approximation analog-to-digital converter (SA-ADC)
A Small-Area and Energy-Efficient 12-bit SA-ADC With Residue Sampling and Digital Calibration for CMOS Image Sensors
Article
10
62
10.1109/TCSII.2015.2457812
932-936
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Kim, Min-Kyu
Hong, Seong-Kwan
Kwon, Oh-Kyong
2015000491
S
COLLEGE OF ENGINEERING[S]
DEPARTMENT OF ELECTRONIC ENGINEERING
okwon